# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#  Library Setup
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

set techlib_path /export/homeO3/techlib/smic180
set std_cell_path ${techlib_path}/SC/aci/sc-x

set target_library  {typical.db}
set link_library    {* typical.db dw_foundation.sldb}
set synthetic_library {dw_foundation.sldb}
set symbol_library  {smic18.sdb}

set search_path [list . ${synopsys_root}/libraries/syn]
lappend search_path ${std_cell_path}/synopsys
lappend search_path ${std_cell_path}/symbols/synopsys

set verilogout_equation false
set verilogout_no_tri true
set verilogout_show_unconnected_pins true
set hdl_naming_threshold 1
set template_naming_style "%s"
suppress_message VER-936
suppress_message VER-130
suppress_message VER-318
history keep 200

echo "\n\nI am ready...\n"

#------------------------------
# set the top design
#------------------------------
set top_design "sfifo"
define_design_lib WORK -path ./analyzed/WORK

#------------------------------
# set the necessary path
#------------------------------
set src        .
set run        .
set log        .
set out        .

#-----------------------------
# set the source file and parition
#-----------------------------
lappend search_path  ${src}

#define_design_lib work -path ${work}

# If you have multiple files to be synthesized, such as you have a.v, b.v, c.v, and d.v,
# you can set sflist as follows
# set sflist {a b c d}
set sflist {sfifo}

#-----------------------------
# read the RTL files
#-----------------------------
foreach module $sflist {
analyze -f verilog -lib work $module.v
}

elaborate ${top_design} > ${log}/${top_design}_elaborate.log

#-------------------------------------
# check the design with DW and gtech
#-------------------------------------
check_design > ${log}/${top_design}_pre_check.log

#--------------------------
# set the current design
#--------------------------
current_design ${top_design} 

#--------------------------
# link
#--------------------------
link
uniquify

#------------------------
# save the flat with DW and gtech
#------------------------
write_file -f verilog -hierarchy -output ${run}/${top_design}_unmapped.v
write_file -f ddc     -hierarchy -output ${run}/${top_design}_unmapped.ddc

#--------------------------
# timing and area
#--------------------------

set_max_area 0

set top_clk         "clock"
set clk_period      "8"

create_clock -p $clk_period [get_ports $top_clk]
set_dont_touch_network [get_clocks $top_clk]
set_clock_uncertainty 0.5 [get_clocks $top_clk]

set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $top_clk]]

set_input_delay [expr $clk_period * 0.6] -clock $top_clk $all_in_ex_clk 
set_output_delay -max [expr $clk_period * 0.6] -clock $top_clk [all_outputs]

#-----------------------------
# set operating environment
#-----------------------------
set_operating_conditions typical
set_wire_load_model -name smic18_wl10
set auto_wire_load_selection false
set_wire_load_mode top

set_driving_cell -library typical -lib_cell NAND2X1 -pin Y $all_in_ex_clk
set_load [expr [load_of typical/NAND2X1/A] * 3 ] [all_outputs]

#-------------------------
# compile
#-------------------------
compile

#change_names
#change_names -rules verilog -verbose -hier
#-------------------------
# check
#-------------------------
check_timing > ${log}/${top_design}_uncon_path.log
check_design > ${log}/${top_design}_check.log

#-------------------------
# save the design
#-------------------------
write_file -f verilog -hierarchy -output ${out}/${top_design}_mapped.v
write_file -f ddc     -hierarchy -output ${out}/${top_design}_mapped.ddc
write_sdf ${out}/${top_design}.sdf
write_sdc ${out}/${top_design}.sdc
write_script -format dctcl -hierarchy -output ${run}/${top_design}.tcl


#-------------------------
# report
#-------------------------
proc cal_freq { clock_period } {
  return [expr 1000/$clock_period];
}
report_clock -skew > ${log}/${top_design}_clk.log
echo "The frequency of the design is :" >> ${log}/${top_design}_clk.log
echo "-----------------------------" >> ${log}/${top_design}_clk.log
echo [cal_freq $clk_period] "MHz" >> ${log}/${top_design}_clk.log
echo "-----------------------------" >> ${log}/${top_design}_clk.log

report_timing > ${log}/${top_design}_timing.log
report_constraints -all_violators > ${log}/${top_design}_con.log
report_reference > ${log}/${top_design}_reference.log
report_area > ${log}/${top_design}_area.log
report_power > ${log}/${top_design}_power.log
report_port > ${log}/${top_design}_port.log

report_lib typical > ${out}/use_lib.message

#-------------------------
# exit
#---------------------

